Exemplary embodiments relate to read methods of a semiconductor memory device and, more particularly, to read methods of a non-volatile memory device.
FIG. 1 is a circuit diagram of a memory cell array for illustrating a conventional read method.
Referring to FIG. 1, a semiconductor memory device includes a memory cell array for storing data. The memory cell array includes a plurality of memory cell blocks. For illustration purposes, one of the plurality of memory cell blocks is shown in FIG. 1. The memory cell block is described in detail below.
The memory cell block includes a plurality of cell strings ST0 to STk. Each (for example, ST0) of the cell strings includes a drain select transistor DST coupled to a bit line BL0, a source select transistor SST coupled to a common source line CSL, and a plurality of memory cells C00 to C0n coupled in series between the drain select transistor DST and the source select transistor SST.
In particular, an interval between the cell strings ST0 to STk of the memory cell block is inversely proportional to an increase in the degree of integration of the semiconductor memory devices. An interval between the memory cells belonging to the same cell string ST0 is also gradually decreased. Here, when additional cells are programmed after target cells are programmed in a program operation, the threshold voltages of previously programmed cells may be changed due to interference generated when the program operation of subsequently programmed cells is performed. A change in the threshold voltages of the memory cells is described in detail below.
FIG. 2 is a graph illustrating above-discussed features with respect to a read method.
Referring to FIGS. 1 and 2, if one of the cells belonging to a first cell string ST1 is a target cell to be read, the threshold voltage of the target cell 14 may be changed depending on the threshold voltages of cells 12 and 16 next to the target cell 14. The threshold voltage of the target cell 14 is changed by interference generated when the program operation of the next cells 12 and 16 is performed. Often, the threshold voltage R0 of the target cell 14 rises to, for example, R0+1. However, the threshold voltage R0 of the target cell 14 may drop to R0−1 depending on the program states of the next cells 12 and 16.
For example, if the next cells 12 and 16 are in an erase state and a third program state or the erase state and a second program state, respectively, or both the next cells 12 and 16 are in the second program state, the threshold voltage of the target cell 14 coupled between the next cells 12 and 16 may drop to R0−1. In this case, if data of the target cell 14 is read using a read voltage Vr, the data may not be accurately read because of cells 22 having respective threshold voltages each lower than the read voltage Vr.